Signal Layer Repair
Solves spacing, annular ring, smd pitch, surface bottleneck and trace width problems using a range of repair methods according to user-defined priorities. Repair methods include trace and bus rerouting, surface shaving, blow-up traces, local trace thinning and more.
Solder Mask Repair
Solves solder mask clearance, bridge and coverage problems with dedicated repairs, both to the solder mask itself or to the related copper on outer layers. Special treatment is provided for fully or partially embedded component pads, SMD and BGA clearances and small or partially covered clearances.
Power and Ground Optimizer
Prevents disconnections and shorts by optimizing power and ground layer clearances and annular rings, without impacting electrical connectivity or compromising manufacturing constraints.
Peelable and Sliver Repair
Finds and fixes slivers in signal, power and ground, and solder mask layers.
Line Width Optimizer
Maximizes yield by achieving optimal line widths without compromising spacing.
Basic Etch Compensation
Protects lines and features from chemical processes. When relevant, increases feature size taking netlist and spacing rules into account. Resolves conflicts by creating a shave down. Available in Shave and Non-Shave modes.
Supports economical and effective chemical processing. Improves thin inner core stability to reduce copper-related waste treatment costs and balances outer layers to ensure uniform copper plating.
Helps avoid resist chips by searching the design for pinholes and automatically repairing them.
Searches each layer for text and nomenclatures, automatically assigning a text attribute to these features. The features are then removed from analyses and automatic edits that do not apply to text. Frees memory by preventing the re-evaluation of the same line group and saves time by reducing false calls.
Silk Screen Repair
The goal of the Silk Screen Repair DFM is to correct possible production problems caused by the graphical elements on Silk Screen Layers. Most common problems found on silk screen layers are: Spacing problems to solder mask, which might cause the legend to be printed on top of the copper in case of misregistration and Text and line widths that are smaller than the production capabilities.
Click to enlarge
Redundant Lines Removal
Removes covered lines from a layer to improve the performance of actions.
Positive Plane Optimization
Increases yield by enlarging isolation around non-connected drills on positively drawn power and ground planes, allowing higher layer registration tolerance.
Solder Paste Optimization
Adjusts solder paste layers to ensure the correct location and proportions of solder paste stencil cutouts.
Drill Touching Copper Count
Extends the life cycle of drill bits by distinguishing between drills according to the number of layers where the drills touch copper.
Neck Down Repair
Eliminates neck down caused by line-to-line and line-to-pad connections by widening lines to achieve uniform line width.
Reduces data size and enables correct analysis by locating drawn lines within the design and replacing them with a single feature.
Net Points Generation
Searches for possible test points in the board’s outer layers. The detected points are inserted into the layer as rectangular, square or round pads, and marked with the generated_net_point attribute.
Set Teardrop Attribute
Automatically recognizes teardrops on customer designs and attributes them accordingly, allowing you to optimize customer delivered teardrops.